Field-effect transistor

  • Inventors: WASA KENJI
  • Assignees: Nec Corp
  • Publication Date: December 02, 1991
  • Publication Number: JP-H03270023-A

Abstract

PURPOSE: To reduce an electrode width occupied on a chip while a current density condition required for reliability is maintained by a method wherein a drain electrode and a source electrode are formed in tapered-shape in such a way that their tip-part width is narrower than their root width on an active layer. CONSTITUTION: Comb-shaped electrodes are formed in tapered-shape in such a way that their tip-part width (b) is narrower than their root width (a). This transistor is constituted of the following: a drain electrode 1 and a source electrode 2 which have been arranged mutually in a comb shape on an active region 4; and a gate electrode 3 which is arranged along the comb-shaped electrodes of the source electrode and the drain electrode which are tapered in shaped. At this time, their root width (a) of the drain electrode 1 and the source electrode 2 is set to a required size by taking into consideration a current density required to ensure their reliability. Thereby, the electrode width of the comb- shaped electrode as a whole can be reduced. Consequently, the size of a chip can be reduced by this reduced width. COPYRIGHT: (C)1991,JPO&Japio

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    JP-2009212460-ASeptember 17, 2009Sumitomo Electric Ind Ltd, 住友電気工業株式会社Semiconductor device
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